View W3EG6433S-JD3_6472325.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 ddr266 and ddr333 double-data-rate architecture bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input. auto and self refresh serial presence detect dual rank power supply: 2.5v 0.2v jedec 184 pin dimm package ? jd3 pcb height: 30.48 (1.20") note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option 256mb C 2x16mx64 ddr sdram unbuffered features description the w3eg6433s is a 2x16mx64 double data rate sdram memory module based on 256mb ddr sdram component. the module consists of sixteen 16mx8 ddr sdrams in 66 pin tsop packages mounted on a 184 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * this product is under development, is not quali? ed or characterized and is subject to change without notice. operating frequencies ddr333@cl=2.5 ddr266 @cl=2 ddr266 @cl=2 ddr266 @cl=2.5 clock speed 166mhz 133mhz 133mhz 133mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2-3-3 2.5-3-3
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary pin configuration pin symbol pin symbol pin symbol pin symbol 1v ref 47 nc 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 nc 3v ss 49 nc 95 dq5 141 a10 4 dq1 50 v ss 96 v ccq 142 nc 5 dqs0 51 nc 97 dqm0 143 v ccq 6 dq2 52 ba1 98 dq6 144 nc 7v cc 53 dq32 99 dq7 145 v ss 8 dq3 54 v ccq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 v cc 11 v ss 57 dq34 103 nc 149 dm4 12 dq8 58 v ss 104 v ccq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ccq 61 dq40 107 dqm1 153 dq44 16 ck1 62 v ccq 108 v cc 154 ras# 17 ck1# 63 we# 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ccq 19 dq10 65 cas# 111 cke1 157 cs0# 20 dq11 66 v ss 112 v ccq 158 cs1# 21 cke0 67 dqs5 113 nc 159 dm5 22 v ccq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 nc 161 dq46 24 dq17 70 v cc 116 v ss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 v ss 72 dq48 118 a11 164 v ccq 27 a9 73 dq49 119 dm2 165 dq52 28 dq18 74 v ss 120 v cc 166 dq53 29 a7 75 ck2# 121 dq22 167 nc 30 v ccq 76 ck2 122 a8 168 v cc 31 dq19 77 v ccq 123 dq23 169 dqm6 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v ccq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ccid 128 v ccq 174 dq60 37 a4 83 dq56 129 dm3 175 dq61 38 v cc 84 dq57 130 a3 176 v ss 39 dq26 85 v cc 131 d30 177 dm7 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 nc 180 v ccq 43 a1 89 v ss 135 nc 181 sa0 44 nc 90 nc 136 v ccq 182 sa1 45 nc 91 sda 137 ck0 183 sa2 46 v cc 92 scl 138 ck0# 184 v ccspd pin names a0-a11 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs8 data strobe input/output ck0, ck1, ck2 clock input ck0#ck1#, ck2# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable dm0-dm7 data-in-mask v cc power supply v ccq power supply for dqs v ss ground v ref power supply for reference v ccspd serial eeprom power supply sda serial data i/o scl serial clock sa0-sa2 address in eeprom nc no connect
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary functional block diagram cs0# dqs0 dm0 dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs1 dm1 dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs2 dm2 dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqs3 dm3 dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqs4 dm4 dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqs5 dm5 dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqs6 dm6 dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqs7 dm7 dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dqs dqs dqs dqs i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dqs dqs dqs dqs cs1# i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 a0 - a11 a0-a11 : ddr sdrams ras# ras# : ddr sdrams cas# cas# : ddr sdrams we# we# : ddr sdrams ba0 - ba1 ba0-ba1 : ddr sdrams v ss ddr sdrams v cc /v ccq ddr sdrams ddr sdrams vref v ccspd spd ddr sdrams *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0# *ck1/ck1# *ck2/ck2# 4 ddr sdrams 6 ddr sdrams 6 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp card edge ddr sdrams ddr sdrams ddr sdrams ddr sdrams ddr sdrams ddr sdrams r=120 ? ck0/1/2 * * cke0/1 cke : ddr sdrams ck0/1/2# notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs# relationships must be maintained as shown. dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# dm# cs# 3. dq, dqs, dm#/dqs# resistors: 22 ohms + 5%. 4. bax, ax, ras#, cas#, we # resistors: 3 ohms + 5%.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 24 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability absolute maximum ratings dc operating conditions recommended perating conditions (voltage referenced to v ss =0v, ta=0 to 70c) parameter symbol min max unit note supply voltage (for device with a nominal v cc of 2.5v) v cc 2.3 2.7 v i/o supply voltage v ccq 2.3 2.7 v i/o reference voltage v ref 0.49*v ccq 0.51*v ccq v1 i/otermination voltage v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih v ref + 0.15 v ccq + 0.3 v input logic low voltage v il -0.3 v ref -0.15 v input voltage level, ck and ck# inputs v in(dc) -0.3 v ccq + 0.3 v input differential voltage, ck and ck# inputs v id(dc) 0.36 v ccq + 0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver); v out = v tt = 0.84v i oh -16.8 ua output high current(normal strengh driver); v out = v tt = 0.84v i ol 16.8 ua output high current(half strengh driver); v out = v tt = 0.45v v oh -9 ua output high current(half strengh driver); v out = v tt = 0.45v v ol 9ua notes: 1. v ref is expected to be equal to 0.5*v ccq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on v ref may not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 4. the ratio of the pullup current to the pulldown current is speci? ed for the same temperature and voltage, over the entire t emperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maximum difference between pullup and pulldown drivers due t o process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary capacitance t a = 25c. f = 1mhz, v cc = 2.5v parameter symbol max unit input capacitance (a0-a11) c in1 81 pf input capacitance (ras#,cas#,we#) c in2 81 pf input capacitance (cke0, cke1, cke2) c in3 50 pf input capacitance (clk0, clk1, clk2) c in4 34 pf input capacitance (cs0#, cs1#) c in5 50 pf input capacitance (dmo ~ dm7) c in6 12 pf input capacitance (ba0-ba1) c in7 81 pf data input/output capacitance (dq0-dq63)(dqs) c out 12 pf data input/output capacitance (cb0-cb7) c out -pf
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary i dd specifications and test conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v includes ddr sdram component only parameter symbol conditions ddr333@cl=2.5 max ddr266@cl=2 max ddr266@cl=2/2.5 max units operating current i dd0 one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 680 640 640 ma operating current i dd1 one device bank; active-read- precharge burst = 2; t rc =t rc (min); t ck =t ck (min); l out = 0ma; address and control inputs changing once per clock cycle. 880 800 800 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck =t ck (min); cke=(low) 24 24 24 rna idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 200 180 180 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke=(low) 240 200 200 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 360 320 320 ma operating current i dd4r burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); l out = 0ma. 1,120 960 960 ma operating current i dd4w burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle. 1,160 1,000 1,000 rna auto refresh current i dd5 t rc = t rc (min) 1,320 1,240 1,240 ma self refresh current i dd6 cke 0.2v 16 16 16 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 2,400 2,000 2,000 ma notes: ? module i dd was calculated on the basis of component i dd and can be different measured according to dq hearing cap. ? i dd speci? cation is based on samsung components. other dram manufactures speci? cation may be different.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions ac characteristics 335 (ddr333@cl=2.5 ) 262 (ddr266@cl=2.0) 263 (ddr266@cl=2.0) 265 (ddr266@cl=2.5) parameter symbol min max min max min max min max units notes row cycle time t rc 60 60 65 65 ns refresh row cycle time t rfc 72 75 75 75 ns row active time t ras 42 70k 45 120k 45 120k 45 120k ns ras to cas delay t rcd 18 15 20 20 ns row precharge time t rp 18 15 20 20 ns row active to row active delay t rrd 12 15 15 15 ns write recovery time t wr 15 15 15 15 ns last data in to read command t wtd 1111t ck col. address to col. address delay t ccd 1111t ck clock cycle time cl=2.0 t ck 7.5 12 7.5 12 7.5 12 10 12 ns cl=2.5 6 12 7.5 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs-out access time from ck/ck t dqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck t ac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to output data edge t dqsq - 0.45 - 0.5 - 0.5 - 0.5 ns 12 read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck ck to valid dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs-in setup time t wpres 0000ns3 dqs-in hold time t wpre 0.25 0.25 0.25 0.25 t ck dqs falling edge to ck rising-setup time t dss 0.2 0.2 0.2 0.2 t ck dqs falling edge from ck rising-hold time t dsh 0.2 0.2 0.2 0.2 t ck dqs-in high level width t dqsh 0.35 0.35 0.35 0.35 t ck dqs-in low level width t dqsl 0.35 0.35 0.35 0.35 t ck dqs-in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time (fast) t is 0.75 0.9 0.9 0.9 ns i,5.7~9 address and control input hold time (fast) t ih 0.75 0.9 0.9 0.9 ns i,5.7~9 address and control input setup time (slow) t is 0.8 1.0 1.0 1.0 ns i,6~9 address and control input setup time (slow) t ih 0.8 1.0 1.0 1.0 ns i,6~9 data-out high impedence time from ck/ck t hz +0.7 +0.75 +0.75 +0.75 ns 1 data-out high impedence time from ck/ck t lz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 input slew rate (for input only pins) t sl(i) 0.5 0.5 0.5 0.5 v/ns input slew rate (for i/o pins) t sl(io) 0.5 0.5 0.5 0.5 v/ns
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions (continued) ac characteristics 335 (ddr333@cl=2.5) 262 (ddr266@cl=2.0) 263 (ddr266@cl=2.0) 265 (ddr266@cl=2.5) parameter symbol min max min max min max min max units notes output slew rate (x4,x8) t sl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns output slew rate matching ratio (rise to fall) t slmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5 ns mode register set cycle time t mrd 12 15 15 15 ns j, k dq & dm setup time to dqs t ds 0.5 0.5 0.5 0.5 ns j, k dq & dm hold time to dqs t dh 0.45 0.5 0.5 0.5 ns 8 control & address input pulse width t ipw 2.2 2.2 2.2 2.2 ns 8 dq & dm input pulse width t dipw 1.75 1.75 1.75 1.75 ns power down exit time t rdex 6 7.5 7.5 7.5 ns exit self refresh to non-read command t xsrd 75 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 200 t ck refreash interval time t refi 15.6 15.6 15.6 15.6 us 4 output dqs valid window t qh t hp -t qhs -t hp -t qhs -t hp -t qhs -t hp -t qhs ns 11 clock half period t qh t clmin or t chmin - t clmin or t chmin - t clmin or t chmin - t clmin or t chmin ns 10, 11 data hold skew factor t qhs 0.55 0.75 0.75 0.75 ns 11 dqs write postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 2 active to read with auto precharge command t rap 18 20 20 20 autoprecharge write recovery & precharge time t xsnr t wr /t ck + t rp /t ck ) t wr /t ck + t rp /t ck ) t wr /t ck + t rp /t ck ) t wr /t ck + t rp /t ck ) t ck 13
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary 9. slew rate is measured between v oh (ac) and v ol (ac). 10. min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum speci? cation limits for t cl and t ch . for example, t cl and t ch are = 50% of the period, less the half period jitter (t jit (hp)) of the clock source, and less the half period jitter due to crosstalk (t jit (crosstalk)) into the clock traces. 11. t qh = t hp - t qhs , where: t hp = minimum half clock period for any given cycle and is de? ned by clock high or clock low t ch , t cl ). t qhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. t dqsq consists of data pin skew and output pattern effects and p-channel to n-channel variation of the output drivers for any given cycle. 13. t dal = (t wr /t ck ) + (t rp /t ck ) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr266 at cl=2.5 and t ck =7.5ns t dal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) t dal = 5 clocks notes 1. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level but specify when the device output in no longer driving (hz), or begins driving (lz). 2. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. the speci? c requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge. a valid transition is de? ned as monotonic and meeting the input slew rate speci? cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high- z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss. 4. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 5. for command/address input slew rate 1.0 v/ns. 6. for command/address input slew rate 0.5 v/ns and > 1.0 v/ns 7. for ck & ck# slew rate 1.0 v/ns. 8. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation.
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) max 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for jd3 * all dimensions are in millimeters and (inches) ordering information for jd3 part number speed cas latency t rcd t rp height* w3eg6433s335jd3 166mhz/333mb/s 2.5 3 3 30.48 (1.20") w3eg6433s263jd3 133mhz/266mb/s 2 2 2 30.48 (1.20") w3eg6433s263jd3 133mhz/266mb/s 2 3 3 30.48 (1.20") w3eg6433s265jd3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) max 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for d3 * all dimensions are in millimeters and (inches) ordering information for d3 part number speed cas latency t rcd t rp height* w3eg6433s335d3 166mhz/333mb/s 2.5 3 3 30.48 (1.20") w3eg6433s262d3 133mhz/266mb/s 2 2 2 30.48 (1.20") w3eg6433s263d3 133mhz/266mb/s 2 3 3 30.48 (1.20") w3eg6433s265d3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg6433s-d3 -jd3 november 2005 rev. 2 preliminary document title 256mb C 2x16mx64 ddr sdram unbuffered revision history rev # history release date status rev 1 1.1 created datasheet 1.2 added lead-free and rohs notes 1.3 added ac specs 1.4 moved from advanced to preliminary 12-04 preliminary rev 2 2.1 added jedec standard pcb 2.2 d3 option is "not recommended for new designs" 2.3 added lead-free and rohs notes 2.4 added source control notes 2.5 added industrial temperature options 5-05 preliminary rev 3 3.1 update ac, i dd and cap specs 3.2 add 333mh speed 11-05 preliminary

▲Up To Search▲

Price & Availability of W3EG6433S-JD3

	To Download W3EG6433S-JD3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .